A phase-locked loop (PLL) is a negative feedback loop where an output phase of a voltage-controlled oscillator (VCO) can be automatically synchronized (“locked”) to a phase of a periodic input signal. The locking property of the PLL has numerous applications in communication systems such as frequency synthesis, frequency, amplitude, or phase modulation-demodulation, and clock and data recovery. A basic PLL has three components connected in a feedback loop: a VCO, a phase detector, and a loop filter, which is generally some type of low-pass filter. A basic PLL additionally includes a feedback frequency divider in applications where the VCO frequency is designed to be a multiple of a frequency of the input reference clock.
The VCO is an oscillator whose frequency is monotonically modulated by an input voltage. The voltage at the input of the VCO determines the frequency of a periodic signal at the output of the VCO. While the frequency of the VCO can be designed to decrease in response to an increase in the voltage input, voltage-controlled oscillators are typically designed so as to increase frequency in response to an increasing input voltage.
The output of the VCO and a periodic input signal are inputs to the phase detector. The period input signal is generally referred to as an input reference clock. The phase detector produces an output voltage signal proportional to the phase difference between the input reference clock and the VCO output signal. The output of the phase detector is filtered by the low-pass loop filter. The loop is closed by connecting the loop filter output to the input of the VCO, such that the loop filter output voltage controls the frequency of the VCO. When the loop is “locked”, the phase and frequency of the VCO output are substantially equal to the phase and frequency of the input reference clock.
For PLL's with low jitter requirements, such as those utilized in high-speed serial data transmission, both coarse and fine control of the VCO are typically required, as a single line control is generally not sufficient. Coarse control provides the tuning range necessary for the PLL to lock to its input reference clock amidst process, power supply voltage, and temperature (PVT) fluctuations; uncertainties in circuit modeling during the design process, and flexibility to adjust the input reference frequency for system test purposes. Fine control, with its smaller effect on the VCO output, allows the PLL to track small perturbations in input and voltage-temperature conditions during normal operation while providing high immunity against circuit noise that principally dictate jitter performance.
One conventional low-jitter PLL configured as a frequency synthesizer employs a charge-pump loop filter providing the fine control voltage input to a varactor-tuned VCO, wherein the charge-pump loop filter is driven by a sequential phase-frequency detector (PFD). One conventional sequential PFD, commonly referred to as cross-coupled quad-NOR gate detector, suffers from an inherent jitter-causing glitch occurring when a rising clock edge occurs while an associate reset signal is asserted. In another basic implementation, the sequential PFD consists of two positive edge-triggered D (delay) latches and a logical AND-gate. The first latch senses rising edges in an input reference clock (REFCLK) and the second rising edges in a feedback clock (FDBCLK) in respectively generating UP and DOWN outputs which serve as control inputs to the charge-pump loop filter. When both the UP and DOWN inputs are asserted. HI, the AND-gate generates a RESET signal that clears both latch outputs concurrently, thereby resetting the PFD for the next phase comparison.
The resulting UP and DOWN outputs are pulses having different pulse widths, where the wider pulse is wider than the narrower pulse by the phase difference between the REFCLK and the FDBCLK. The wider pulse also corresponds to the clock having the earlier rising edge. The width of the narrower pulse is determined by propagation delays in the AND-gate and associated reset circuitry. When the REFCLK has a higher frequency than the FDBCLK, the UP pulse is wider, resulting in the charge-pump loop filter raising its output voltage and the corresponding VCO increasing the frequency of FDBCLK. When the FDBCLK has a higher frequency than REFCLK, the DOWN pulse is wider, resulting in the charge-pump loop filter lowering its output voltage and the corresponding VCO decreasing the frequency of FDBCLK.
The above describes the normal operation of the PLL. However, in a PLL employing coarse and fine control of a varactor-tuned VCO, a self-calibration procedure is invoked prior to normal operation. Employing both coarse and fine control desensitizes the PLL from circuit noise affecting the control voltage. Self-calibration refers to a process for determining a level of the coarse control voltage input that will set the VCO in the correct frequency range (“capture range”) so that the PLL can track the input reference clock using only the fine control voltage input. Ideally, the self-calibration procedure is performed with the PLL in an “open-loop” configuration, with the charge-pump output held at a constant value. The coarse control input is then “swept” across a voltage range to find a voltage level that will cause the VCO to generate a frequency that is within the PLL's frequency capture range. By doing so, the PLL should be able to track input perturbations using only fine control.
One calibration method involves positioning a switch in the fine control voltage path between the charge-pump loop filter and the VCO. The switch is opened during the self-calibration procedure to achieve the open-loop condition and to isolate the VCO from the charge-pump output. However, during normal operation, the switch adds resistance to the loop and negatively impacts loop performance and response.
One feature beneficial for a PLL is that it be testable. The functionality of PLL components can be verified by observing the VCO output for a given set of “forced” phase-frequency detector outputs. Controlling the PFD outputs can also aid in isolating faulty components in the loop. It is possible to incorporate testability in the sequential PFD by replacing the edge-triggered D-latches described above with corresponding scan latches whose outputs can be overridden with external scan chain data. However, this technique, commonly employed in read-write functionality testing of registers, cannot be applied in a PLL because the PFD must not only operate in its override mode during scan testing mode, but also during PLL self-calibration.